The control electronics — AWG, FPGA, cryo-CMOS pipeline

Why control electronics is the real bottleneck

People ask about qubit count. The honest answer is that qubit count is cheap compared to the control stack behind it. A 100-physical-qubit transmon machine needs, at minimum, 100 individually shaped microwave drive lines for X/Y rotations, 100 flux bias lines for frequency tuning, a readout chain per resonator bus (typically multiplexed eight-to-twelve qubits per feedline), and the digital fabric to coordinate all of it inside the coherence budget of the device — roughly 100 microseconds of T1 and rather less T2 at the chip face. Miss the timing by tens of nanoseconds, miss the amplitude calibration by a fraction of a percent, and the gate fidelity collapses below the surface-code threshold. The control electronics — the AWG, FPGA, and increasingly cryo-CMOS pipeline — is where a quantum computer is actually built or lost.

This page sets out the engineering position we are taking for Ireland Quantum 100 ahead of cryostat install in Q4 2026. None of this is exotic by research standards. All of it is hard to integrate at production discipline.

The arbitrary waveform generator and the IQ chain

Single-qubit gates on a transmon are driven by shaped microwave pulses at the qubit's transition frequency, typically in the 4–7 GHz band. The shaping itself happens at baseband — usually a DRAG-corrected Gaussian or cosine envelope on the order of 20–50 ns — generated by an arbitrary waveform generator at 1–2 GS/s on each of the I and Q channels, then upconverted via an IQ mixer against a CW local oscillator. The DRAG correction, which subtracts a derivative term on the quadrature channel to suppress leakage into the |2⟩ state, is the difference between a 99.9% gate and a 99.0% gate. It is not optional.

Two-qubit gates on a fixed-frequency transmon lattice are driven either by cross-resonance microwave tones or, for tunable couplers, by carefully timed flux pulses on a separate DC-coupled AWG channel. Flux AWGs are usually slower (typically 1 GS/s, 14–16 bit) but demand much tighter DC stability — drift of a few hundred microvolts on a flux line will move the qubit frequency enough to break a calibration overnight. Mains-induced 50 Hz pickup on a flux line is a real and chronic problem; the cabling, filtering, and grounding layout from rack to mixing chamber is engineering, not physics.

The FPGA layer and real-time feedback

The quantum FPGA layer is what turns a pile of waveform generators into a coherent computer. Three jobs sit on the FPGA fabric:

• Sequencing. Dispatching pulse envelopes, phase updates, and frequency shifts across dozens of channels with sub-nanosecond skew between channels. Phase coherence between drive and readout has to be maintained across the whole experiment, which means a single low-jitter clock distributed across every chassis with locked deterministic latency.
• Readout demodulation. The dispersive readout signal at 6–8 GHz is downconverted, digitised at typically 1 GS/s, and digitally demodulated against a matched filter to produce a single complex IQ point per shot. That demodulation has to happen on-FPGA inside a few hundred nanoseconds if it is to feed back into the next gate.
• Mid-circuit feedback. Surface-code error correction is not a post-processing step. Syndrome measurements are decoded and conditional Pauli frame updates are applied while the data qubits are still in the middle of the circuit. The decode-to-decision latency budget is on the order of one microsecond. That is an FPGA problem, eventually an ASIC problem, and not a CPU problem.

For the 100-qubit machine we are targeting an OpenQASM 3 front end, with the real-time control flow (if, while, mid-circuit measurement) compiled down to FPGA microcode. Qiskit, Cirq and PennyLane will sit above that as user-facing SDKs. Pulse-level access — the equivalent of Qiskit Pulse — will be available for calibration and for groups doing their own gate design.

Cryo-CMOS and where the control stack is going

The room-temperature approach — racks of AWGs feeding coax bundles down through the dilution refrigerator — does not scale past a few hundred qubits. Each coax line is a thermal load. Each line is a calibration target. The wire count alone becomes the limit. Cryo-CMOS is the answer the field has converged on: move the control electronics down the fridge, ideally to the 4 K stage where cooling power is on the order of a watt, and in the longer term to the 100 mK stage where it is a few hundred microwatts.

The engineering reality of cryo-CMOS is hard. Standard 22 nm and 28 nm bulk and FD-SOI processes do operate at 4 K, but threshold voltages shift, mobility changes, and 1/f noise behaves badly. Phase noise on a cryogenic local oscillator has to be low enough not to dephase the qubit it is driving, which is a non-trivial constraint when the power budget is a few milliwatts per qubit. We are not building our own cryo-CMOS silicon for the first 100-qubit system — that would be a five-year detour. We are designing the control rack and fridge wiring so that the 4 K stage can host third-party cryo-CMOS multiplexers and, later, cryo-CMOS drive ASICs as they mature, without re-plumbing the machine.

Calibration, drift, and the operational reality

A 100-qubit transmon system has, very roughly, several thousand calibrated parameters: qubit frequencies, anharmonicities, single-qubit pulse amplitudes and DRAG coefficients, two-qubit gate amplitudes and phases, readout frequencies and discrimination thresholds, crosstalk compensation matrices. They drift. TLS defects shift qubit frequencies by tens of kilohertz over hours. Cosmic-ray events cause correlated errors across a chip. Calibration is therefore not a startup procedure but a continuous background process running on the FPGA layer, with full re-characterisation cycles scheduled into the operational rota.

For the climate-science workloads that are the first cohort on the machine — VQE and ADAPT-VQE for amine and MOF carbon-capture chemistry, perovskite electronic structure for photovoltaics, lithium and sodium electrolyte modelling for batteries — circuit depths in the early multi-qubit phase will be modest, and quality of two-qubit gates matters far more than raw count. The control stack is what delivers that quality.